1. Field of the Invention
The present invention relates to a gradation controlled LED display device having a matrix of LED chips and a method for controlling the lighting time of each of the LED chips so that each LED chip may provide a gradation level corresponding to the lighting time.
2. Description of the Prior Art
Among display devices including color television sets, those employing a matrix of LED chips are widely used because they have a relatively long service life and are easy to form a large screen by combination of a plurality of display units each having the matrix of LED chips. In particular, gradation controlled LED display devices that control the lighting time of each LED chip to display gradation levels are spotlighted.
FIG. 1A is a block diagram showing a gradation controlled LED display device according to a prior art. An LED array 101 has LED chips 101a of three primary colors, or the red (R), green (G), and blue (B) colors that are arranged in a triple matrix consisting of R, G and B 16.times.32-dot matrices. A data input control circuit 103 receives R, G, and B display data each of 8 bits in response to a clock signal CK1 while a select signal SE is being high. The 8-bit display data for red consists of bits RA to RH, that for green GA to GH, and that for blue BA to BH. These R, G, and B display data pieces are supplied to RAMs 105R, 105G, and 105B, respectively. Each piece of 8-bit display data corresponds to a dot and represents one of 255 gradation levels. The RAMs 105R, 105G, 105B accumulate 8-bit display data for 32 dots each and supply them to a gradation control circuit 107. According to the display data, the gradation control circuit 107 controls the lighting time of each LED chip so that the LED chip may provide one of the 255 gradation levels. A data driver 109 receives the gradation controlling display data from the gradation control circuit 107 and simultaneously drives 96 (32 each for R, G, and B) LED chips 101a according to the display data.
A reset signal RE resets 4-bit counters 111a and 111b, which are arranged in two stages and operate in synchronization with the clock signal CK1. The output of the 4-bit counter 111b is given to a 4-to-16 decoder 113, and the output of the decoder 113 is given to a scan driver 115. The scan driver 115 sequentially scans the LED chips 101a, 96 at a time, whenever the data driver 109 drives 96 of the LED chips 101a.
FIG. 1B shows the details of the red matrix of the LED array 101. The LED array 101 includes 3.times.32=96 data lines p1 to p96 and 16 scan lines s1 to s16. The red matrix corresponds to data lines p1 to p32. The green and blue matrices correspond to data lines p33 to p64 and p65 to p92 respectively. The data line p33 neighbors to data line p1. The data line p65 neighbors to data line p33 so that the data lines p1, p33 and p65 constitute a set of data lines. The data lines p2, p34 and p66 constitute another set of data lines. The LED chips 101a are connected to the data and scan lines at the intersections of these lines. The data lines are connected to output terminals of the data driver 109, and the scan lines are connected to output terminals of the scan driver 115.
FIG. 1C is a time chart briefly showing the operation of the red matrix in the display device of FIG. 1A. At t1, a pulse of the reset signal RE resets the 4-bit counters 111a and 111b. At t2, the select signal SE becomes "high" to activate the data input control circuit 103. At t3, a bright signal BR (not shown in FIG. 1A) becomes "high" to disable a display operation.
At t4, a first pulse of the clock signal CK1 rises. In synchronization with the first to 32nd pulses of the clock signal CK1, the data input control circuit 103 fetches R display data pieces of 8 bits, and the RAM 105R accumulates the display data for 32 dots for the first scan line s1. Although now shown in FIG. 1C, the data input control circuit 103 also fetches G and B display data pieces each of 8 bits, and the RAMs 105G and 105B accumulate the display data for 32 dots each, for the first scan line s1.
Between t5 and t6 where the bright signal BR is "low", the display data for the scan line s1 are transferred to the gradation control circuit 107, which controls the gradation levels of the red LED chips in the scan line s1 according to the display data. The gradation controlling display data are supplied to the data driver 109, which drives the red LED chips 101a in the scan line s1 that is scanned by the scan driver 115. As a result, the red LED chips in the scan line s1 display gradation levels based on the display data.
A period between t6 and t7 resembles the period between t3 and t5. Namely, the RAM 105R accumulates display data for 32 dots for the second scan line s2, and the red LED chips in the scan line s2 display gradation levels corresponding to the display data after t7 when the bright signal BR becomes "low". Similarly, display data pieces are supplied and displayed up to the scan line s16. When the select signal SE becomes "low" at t8, the red LED chips in the scan line s16 display gradation levels, and the operation of the data input control circuit 103 terminates.
FIG. 1D is a circuit diagram showing one of 96 unit circuits that form the data driver 109. The unit circuit consists of an npn bipolar transistor 117, a pnp bipolar transistor 119, a first base resistor 121, a bypass resistor 123, a current limiting resistor 124, and a second base resistor 125. The unit circuit also has an input terminal 127 connected to the gradation control circuit 107, and an output terminal 129 connected to one of the data lines.
When the input terminal 127 receives a display signal of "high" from the gradation control circuit 107, a base current flows through the first base resistor 121 to turn on the npn transistor 117. As a result, a current flows from a power supply through the bypass resistor 123, second base resistor 125, and transistor 117, to turn on the pnp transistor 119. This makes the output terminal 129 "high" to activate the corresponding data line.
FIG. 2 shows the lighting times of some of 255 gradation levels controlled by the gradation control circuit 107. Ideally, the fall and rise of each lighting time must involve no delay time as indicated with a dashed line. However, each lighting time involves actually a rise delay of .alpha. as indicated with a solid line. The representative value of a is one to two micro seconds.
This rise delay is caused because the turn-off characteristic of each pnp transistor 119 of the data driver 109 is poor. In the data driver of the conventional gradation controlled LED display device, the resistance of the second base resistor 125 is small, and a large base current flows to the pnp transistor 119, which cause the storage delay time associated with the excursion of the pnp transistor 119 into the saturation region.
As is apparent in FIG. 2, the rise delay or the turn-off time .alpha. is constant on every gradation level. Among 255 lighting times to display 255 gradation levels, the ratio of the turn-off time a to the lighting times becomes larger toward lower gradation levels, in particular, gradation levels 1 to 7. The representative lighting time for the lowest gradation level (level 1) is 0.1.about.0.5 micro second. This is the reason why the conventional display devices are incapable of clearly displaying low gradation levels with required brightness. As shown in FIG. 3, the conventional display devices are incapable of securing good linearity in relative brightness at lower gradation levels.
To improve linearity in relative brightness at lower gradation levels, the turn-off characteristic of the pnp transistor 119 must be improved. It may be possible to employ a uniform large base resistance 125 for each pnp transistor 119 so as to reduce the turn-off time. But, we must consider the thermal limitation of the matrix of LED chips, in which a multitude of heat generating elements are assembled in a limited area. If the operation points of all the pnp transistors 119 always reside in the active region which requires a higher collector voltage (V.sub.C E), by using the uniform large base resistance, the total thermal energy generated by these transistors becomes very large because the transistor in the active region dissipates large power. Then the reliability of the display device may be deteriorated. Further, the value of the current limiting resistor 124 must be enlarged to assure a stable operation of the display device, which requires a larger supply voltage and increases the power dissipation of the data driver 109, in general, to deteriorate the reliability further. As a result, the employment of the uniform large base resistance 125 is not a preferable circuit configuration.